Verilog

Behavioral Floating Point Primitives in Place

I have a first version of high-precision floating point primitives coded up in Verilog. Different from a standard IEEE 754 library, those floating point numbers use a 17-bit mantissa, which works much more efficiently with 18x18 bit multipliers as usually available on FPGAs. In addition, the primitives use an unpacked format, thereby reducing the operations necessary to bring values into the arithmetic operation and to prepare the result. Read More...